The Design And Verification Of Smartcard Based On 8-bit Micro Controller

With the development of chip technology and the improvement of security requirements of applications, smart cards are often used in different applications that require strong security protection and authentication, such as identification, banking, and transportation.Super security, mobility and portability are the development trends of smartcard. The functions of the current smartcard are restricted by its hardware structure, merely satisfying basic requirements.This paper work over the design and verification of Smartcard based on 8051 CPU core through Verilog language. We select the exploitation instrument VCS and DA(Synopsys company), in this environment, I completed the coding design, synthesis, place and route, mapping and timing analysis of the system.By using the VCS and Nc-verilog(Candence company) tools, functional verifications and timing simulations were fulfilled. Thus, the micro controller Smartcard compatible with the msc-8051 instruction sets is completed.First, the system structure is introduced, design the soft core that satisfied all the functional and timing requirements of standard Intel mcs-8051. Then, set this CPU as system core, other modules are designed.The thesis introduced the internal architecture, design method and coding style of the whole system. Then it detailedly introduces the design of every module and the verification method. After that, the thesis shows the implementing results and the timing simulation oscillograms.While designing the system, we spent a lot of time in considering how to divide and define each module and how to coordinate and interconnect these modules.l followed the top—down method to design. First defined the top module, and then divided the top module to several independent small units. In the internal small unit, I design the control signal and the operation of appointed unit according to function and timing demand. As for the interconnection of modules, I defined the interface signal to communicate between them. When I construct the logic, we pay more attention to make the soft design close to the hardware, and I give adequate thought to the proper use of resources and the characteristics of verilog language, so I can effectively make use of hardware resource on FPGA and get a high speed with a low hardware spending to satisfy the demand of the cost and performance.Simultaneously, this paper discussed the verification method used in system chip. I seperately analyzed the single IP verification and the integrated verification method of SoC(system on chip), at the end, the results of simulations and synthesis are given. In recent years, using HDL (hardware description language)to design digital electronics system is a very popular method. Almost in all system design we integrate IP core such...