| To limit a carry-propagation in addition, a redundant binary number adder is proposed. With these adders, a new multiplier is designed. This multiplier processes 4-bit data at a time for the multiple generation. Therefore, the number of partial products is reduced by one fourth. For a fast and accurate division process, a reciprocal unit (RU) is devised, which is based on an accurate linear approximation with a modified bipartite table generation method. Using this new adder, multiplier and reciprocal unit, a new floating-point division algorithm and its design are proposed. For parallel operation, the dividend is separated by two groups of bits that are multiplied with the reciprocal of the divisor to form two separated quotients. A correction term is added to the second quotient form. These quotients are added to make a final quotient. All intermediate results maintain the accuracy of a quarter ulp (unit in the last place). The final quotient maintains only 55 bits for a 53-bit fraction of the IEEE-754 double precision format before rounding. No special rounding algorithm or hardware is required for this floating-point divider since the accuracy is accurate enough to produce the final quotient without error. This floating-point divider is applicable to a high performance coprocessor. |
