The Research Of Pairing-based Cryptography Algorithms And Its Implementation On FPGA Platform

Bilinear pairing is an emerging research area of asymmetric encryptions,and has drawn more attentions in the field of cryptography.Compared with traditional public key cryptosystems such as RSA and ECC,pairing based cryptosystem has the advantages of short key,small storage space and high security.With these features,researchers have developed the identity-based cryptography(IBC),which avoids the problems of authentication and key escrow by trusted third parties.Since the publication of IBC standard SM9,bilinear pairing has become a research hotspot with a wide application foreground.However,the computation of pairing is more complex than and need deep understanding of algebraic structures.The optimization of pairing algorithm and its hardware implementation are still under developing.This thesis aims to design a hardware implementation of pairing algorithm based on FPGA with high speed and less hardware cost.First,the paper reviewed the development of pairing based cryptography.Then mathematical structures such as elliptic curve and finite field were discussed,which are the key constructions of pairing computation.To achieve higher speed,optimization technics of top level algorithms such as Miller loop and Final Exponential is analyzed.We proposed a high parallel architecture of prime field arithmetic unit by using Karatsuba decomposition method of Montgomery algorithm.On this basis,we accomplished the hardware design of bottom operations in Verilog HDL.Finally,Optimal-Ate Pairing on BN curves is successfully implemented on Xilinx vertex-5 FPGA.We verified the correctness of the implementation by comparing with the outcome of magma algebra tool.The result shows our design complete the Optimal-Ate Pairing in 254,853 cycles with hardware costs of 4380 Slices and 131 DSPs,which has effectively improved the computation speed under limited hardware resources.