Design Of High-speed Data Acquisition Board Based On PCI Bus

With the rapid development of LSI (Large Scale Integration) and computer science, digital technology has penetrated into every field of knowledge. As most physical signals in the nature are analog signals, the conversion from analog signals to digital signals has become the key step in the process of signal processing and analysis control. Data acquisition system converts analog signals to digital signals, which can be recognized by computer.Traditional data acquisition system is designed based on ISA bus, but with the limits of its bandwidth, it is difficult to perform high-speed data transmission. PCI local bus, with its outstanding capability and excellent adaptation, has resolved this problem and become the main bus in the computer. PCI bus-based data acquisition system has played a dominant role in high-speed data acquisition. Meanwhile, traditional data acquisition board uses SRAM or SDRAM as data buffer. As SRAM has low capacity and high cost, while SDRAM has low cost and limited transmission bandwidth, DDR SDRAM is adopted as data buffer in this paper, which has merit of high speed, high capacity and low cost.PCI bus-based high-speed data acquisition board, including hardware design and driver program, is researched in this paper. Features of DDR SDRAM, basic configuration and timing of DDR controller, together with basic configuration and timing of PCI bus, are discussed first, while basic theory and development process of FPGA are introduced. Then each module on PCI bus-based high-speed data acquisition board is detailed designed. FPGA is adopted to realize functions of DDR controller and PCI bus controller in this paper. The accession of DDR controller as data buffer is an effective measure to enhance the sampling frequency of data acquisition. Data after A/D conversion will be stored in DDR SDRAM through DDR controller, and then the stored data will be transmitted by PCI bus to upper computer for processing. The whole board realizes functions of signal sampling, data storage and data transmission. The schematics and Verilog source program of timing logical design using FPGA are presented in the paper. At the end of the paper, development of driver program WDM for PCI bus-based data acquisition board is mentioned.Through simulation test, the sampling frequency of the board can reach 250 MSPS, while storage capacity can achieve 1 GByte.