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Design And Implementation Of High-speed Data Acquisition And Editing Controller Based On FPGA

Posted on:2021-02-06Degree:MasterType:Thesis
Country:ChinaCandidate:W W LeiFull Text:PDF
GTID:2428330602965485Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
The acquisition of high-speed data is an important part of flight test.Based on the "development of the acquisition and editing controller in a telemetry system" project,this paper designed a high-speed data acquisition and editing controller based on FPGA.The device is used to collect,encode and transmit multiple analog data and digital data during flight tests,and effectively control the memory get into the corresponding working state.These test data are of practical significance to the design,verification and calibration of the aircraft,and are also a direct source of data for the improvement and development of new aircraft.This article first introduces the system composition which the acquisition and editing controller belongs to and the main function,and designed analog acquisition card,digital card,main control card and power card according to modular design principles.Secondly,start to introduce the hardware circuit.The equipment uses FPGA as the main controller,signal conditioning circuits,analog switches,digital-to-analog converters and its peripheral circuits to complete the collection of analog data.The two channels of PCM data are received through RS-422 interface as well as the sending and receiving of instruction information and status information.Signal conditioning technology is used in the LVDS data transceiver circuit to equalize and pre-emphasize the LVDS signal to meet the design requirements.Then,in the logic design part,introduced the multi-channel analog acquisition logic design based on ROM table,the design of digital transmit and receive logic,the design of multiple data acquisition and packaging methods based on mixed frame technology and time division multiplexing technology,and the design of an feedback error correction mechanism based on 8B/10 B +CRC to improve data link reliability.Finally,a test platform was built to test the function and performance of the device.The test results show that the device can effectively perform data acquisition and framing,and can transmit 100 meters of error-free transmission at a data transmission rate of 240 Mbps.The device works stably and meets the task requirements,And the device has been successfully applied to an aircraft.
Keywords/Search Tags:FPGA, Data acquisition and editing, PCM, LVDS, 8B/10B codec, CRC checksum
PDF Full Text Request
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