Research On Physical Design Of Media SoC/IP

In the last decade, feature size continues scaling down steadily and the number of transistors on a single chip soars. All of this indicates semiconductor industry's prominent development. In order to satisfy design demands, new SoC/IP design methods are adopted by more and more designers while the traditional ASIC(Application Specific Integrated Circuits) methods are obsolete. Because of big size of chip and huge number of transistors, physical design of chips faces more difficulties ever, meanwhile, multimedia applications have been popular and media SoCs aimed to video/audio applications catch the attention of designers. In this paper, we introduce a media SoC - MediaSoC serials, which are developed by the Department of Information Science and Electronic Engineering in Zhejiang Unversity independently. MediaSoC consists of two programmable processor cores: a RISC core RISC3200 and a RISC/DSP core MediaDSP3200. For the application of media processing, MediaSoC also includes some ASIC modules such as TV encoder, memory controller, DMA controller, and other interface units. The chip referred by this paper has been successful fabricated in 0.18μm technology by first time, the test result shows that MediaSoC can be widely used in a rage of multi-media application, such as signal processing, real-time audio/video playback and image processing.The implementation and verification of media SoC are difficult because of its complicated architecture and advanced fabricated technology. This paper takes MediaSoC for example; mainly discuss the physical implementation metal connections and IP(Intellectual Property) design for media SoC. The main contents and works in this paper include:Fast prototyping methodology used in backend implementations in MediaSoC. As traditional flow in SoC design is efficient in consumed time and final results, a new implementation method should be adopted to overcome the issues introduced by high complexity. Referring to silicon virtual prototyping methodology and our experimentation, we introduce a new flow based on normal tools. Using this method minimize design cycle and reach a good result.Wire delay in 0.18μm process technology and below plays an important role in total delay. The gate intrinsic delay and the wire delay and their relative models are described in this chapter, and especially, the crosstalk introduced by coupling capacitances between wires are stressed and the repair method is also given.IP is basic element in SoC design as it connects higher architecture and lower gate utilization. A good IP should be reusable, maintainable and legible. Documentations and models should be intact and elaborate. As a case example, a high performance using 4 pipeline MAC (Multiply-Accumulate accumulator) is hardened in 0.13um process technology.