Parasitic Extraction And Timing Calculation Of Digital Integrated Circuit For Physical Design Stage

Currently with the technology scaling, the parasitic parameters of the interconnects have become dominant influencing the performance of VLSI circuits. For effective placement and route of VLSI circuits, parasitic extraction and timing analysis with high precision are required to provide guidance for them. In this thesis parasitic extraction and timing calculation respectively in pre-route and post-route stage are investigated.For faster timing closure, a parasitic extraction method is developed based on 2D pattern-library method for the pre-route VLSI design. This method generates virtual route and estimates congestion using the placement information of standard cells, and then extract the interconnect parasitics with the pattern-library method. The techniques of generating parasitic RC tree according to the improved FLUTE algorithm, and capacitance extraction of route segment considering congestion are presented. Experiments are carried out on industrial design cases, whose results show that the proposed method has high computational speed and comparable accuracy as commercial tool.Parasitic extraction and timing calculation for post-route are investigated in this thesis. Ac-cording to real routing topology and signal transmitting direction, we can implement the parasitic extraction and timing calculation. With 2.5D capacitance pattern, the capacitance pattern database is created. The unit length parasitic capacitance of wire segment is obtained with the fitting formula produced using the capacitance database.