Hardware Approach To Lifting Based Discrete Wavelet Transform

The discrete wavelet transform(DWT) is useful in many different fields, including signal analysis, signal compression, pattern recognition, and numerical analysis, especially in image/video compression. The DWT decomposes signals into different frequency bands, and performs a multiresolution analysis.Because the traditional DWT is composed of filters, the complexity of VLSI implementation is very high. In 1996, lifting-based DWT is proposed. The advantages of the lifting-based DWT are lower implementation complexity and less hardware resources. The lifting-based DWT is also used in the newest image standard, such as JPEG2000.In this thesis, a new 2-D DWT architectures based on lifting scheme is proposed. In the first part, we present basic architecture for 2-dimensional lifting-based DWT. Because of down-sampling of the DWT, the hardware utilization is very low. In order to solve the problem, we propose a pipelined and parallel architecture that combines the horizontal and vertical DWT together. In the second part, we solve several key problems in the hardware architecture of wavelet. The proposed architecture computes 2-D DWT coefficients concurrently, and achieves higher hardware utilization.The proposed VLSI architectures are described in Verilog HDL, simulated by Modelsim, and synthesized by Synplify.