Design And Implementation Of VLSI Architecture For Lifting-based Discrete Wavelet Transform

Due to the well time-frequency decomposition, the wavelet transform has been extensively used in many applications. The discrete wavelet transform (DWT) has been adopted as the transform core in emerging image compression standard JPEG2000. Since the lifting scheme has several advantages for implementation, it is valuable to design the VLSI architecture for the lifting-based DWT.Firstly the basic theory of wavelet transform, especially the lifting scheme, is presented in this thesis. Then we propose a new formula of the lifting algorithm, leading to a novel form for the lifting scheme. Due to this form, the intermediate data which are used to compute the output data are distributed on different paths. Thus, we can process those intermediate data in parallel by employing the parallel and pipeline techniques. With the above operations, the conventional serial data flow of lifting-based DWT is optimized into parallel one. Thus, the corresponding direct architecture has short critical path latency and is of repeatable. Further, utilizing this repeatability, the efficient folded architecture (EFA) is derived from the direct architecture by employing the fold technique. With this proposed EFA, the required hardware resource is reduced and the hardware utilization is increased greatly. Additionally, we also optimize the scale normalization step of the two dimensional DWT by merging the scale normalization steps of the one dimensional row and column transform. Thus the hardware resource is further reduced. Based on the above operations, this thesis proposes efficient VLSI architecture for 9/7 and 5/3 lifting-based DWT.On the basis of the architecture for the lifting-based DWT, the thesis simulates and implements 5/3 lifting-based DWT on the Altera Stratix II FPGA EP2S15F484C5, using the QuartusII7.0 platform. The software simulation using MATLAB7.1 is also presented to verify the hardware simulation results. The compression and synthesis results indicate the efficiency of the VLSI architecture proposed in this thesis.