The Research On Efficient VLSI Architecture Of Two-dimensional Discrete Wavelet Transform In JPEG2000

JPEG2000 is the next generation image compression standard. Being different from the JPEG standard, it adopts the two-dimensional discrete wavelet transform (2D DWT) while the JPEG adopts the discrete cosine transform. Because of the computation complexities of the discrete wavelet transform, the chip implementation is necessary in many real-time systems. The lifting scheme is the method to construct second generation wavelets. Compared to the Mallat algorithm, it has the advantages of less computation time, in-place operation and so on, so the JPEG2000 standard recommends the lifting scheme to compute the discrete wavelet transforms. Two kinds of filter are recommended in the JPEG2000 standard. One is the 5/3 filter which is used in the lossless image compression, the other is the 9/7 filter which is used in the lossy image compression.After research of the JPEG2000 standard and the theory of wavelet transform, an efficient VLSI architecture based on the lifting scheme of two-dimensional discrete wavelet transform is proposed and illustrated in detail for the 9/7 wavelet transform. In this architecture, the row transform and the column transform are running simultaneously, that is, the column transform starts immediately after two row transforms have finished. In the traditional way that the column starts after all row transforms have finished, the column transform operates along a column. On the contrary, the column transform operates along a row in this architecture. In order to run the row transform and column transform simultaneously, a row transform buffer is placed between the row transform and the column transform. It's implemented in shift register form and easy to control. In addition, several way are adopted to optimize the one dimensional transform architecture. Improving the architecture resulting from the standard lifting scheme reduces the critical path delay; An embedded boundary extension algorithm is adopted instead of the standard symmetric extension and it's easier to implement; The pipeline technique is adopted to increase the speed of processing; Coefficients of the multipliers are transformed into CSD forms and the multiplications are substitute by minimum shift-add operations. Finally this architecture is described at the register transfer level(RTL) using the VHDL language. The results of simulation are identical with those of matlab simulation and thus the validity of this architecture is proved.