The Design Of High-Speed Data Acquisition System Based On CPLD

The paper is under the background of 'Narrow-pulse Time Domain Reflectometry' (Narrow-pulse TDR). Based on the characteristics of the wave, the paper realize the high-speed data acquisition by means of acquire a fixed wave many times and data processing. In addition, the paper mainly discusses and analyzes the theory and structure of high-speed data acquisition system andante-jamming technology.The high-speed data acquisition system uses low speed sample rate A/D converter and low speed memorizer. The system generates time sequence by the counter and control module. The system control the low speed sample rate A/D converter and low speed memorizer via the time sequence. At last, the paper describes the control strategy of the A/D converter and memorizer by using the VHDL (VHSIC hardware description language) based on CPLD (Complex Programmable Logic Device).As a consequence, there are hardware design picture and PCB chat in the appendix of the paper.In the end, the high-speed data acquisition system uses low speed sample rate A/D converter and low speed memorizer, so the system has simple hardware and low cost Because of using ISP (In System Programable) technology, it makes develop project more rapid and makes modify hardware circuit more easy. So combined with use of soft ware, the high-speed data-acquisition system can improve the test precision of the Narrow-pulse TDR and similar test system. Because of its high capability and low cost, it can be used in many fields widely, such as: image manipulation, high-precision video, digital storage oscillograph, cable fault location, national defence, aerospace industry and communications.