Research On Automatic Routing Methodologies For Analog And Mixed-Signal Integrated Circuits

With the booming technology of integrated circuits, the proportion of analog and mixed-signal circuits in a chip is increasing rapidly; however, traditional automatic layout generators for analog ICs generally derived from the similar systems for digital ICs, so they did not involve the careful concerns about the performance of analog circuits, and the requirements of design of analog IC did not satisfied well. In such a case, some automatic routing methodologies for analog and mixed-signal IC have been introduced in this dissertation, to solve the problem of automatic routing, which is one of the topics in the field of layout automation. Given the"performance"of analog IC and the"efficiency"of the router for it, the dissertation illustrates two complete automatic routers, in which there are some algorithms with constraints of performance of analog circuits. By the research mentioned by the dissertation, four contributions are made.1. A net-classification based automatic routing methodology is proposed, and then a complete routing system is implemented. In view of the symmetry and matching constraints of analog circuits, the router converts those constraints to the information of classification, and routes different types of nets by different routing algorithms. In the experimental results, the requirement of symmetry and matching is met, and the total routability of the circuit generally exceeds 98%.2. In face of the requirement of variable wire widths, a routing algorithm, called Multi-Step Maze Algorithm, is proposed. Breaking the confine of single step of traditional Maze algorithm, such an algorithm allows the router to choose different steps in the expansion phase, according to the wire width and pitch of different nets. Not only does the algorithm be suitable for the requirement of variable wire widths, but it benefits for making full use of routing resources. In the experiment result, routability of the algorithm is always 99% or above. 3. To avoid the abuse of routing resources in the routing process, a performance-driven probabilistic resource allocation algorithm is designed to plan and allocate the available resources. This algorithm integrates performance constraints of analog circuits into the process of resource allocation, so that the routing resources are allocated reasonably, with all the performance constraints meted, such as the constraints of symmetry and variable wire width. The algorithm added into the routing system, the routability of critical nets is generally improved 10-20%, and the total routability is improve more than 5%.4. For improving the routing efficiency, a parallel routing system for mixed-signal integrated circuits is proposed. In the system, a novel region partition algorithm considering the factor of load balance is involved, and the serial and parallel modules are well-organized to speed the routing process. Besides, features of multi-core architecture are fully considered and used to improve the execution efficiency of CPU. The experiment result demonstrates that the speedup of the parallel router is almost more than 1.5 in the Dual-Core system, with the routability and wire length same as those of the routing result of a serial router.