The Front-end Design And Verification Of Scaler Chip For Flat Panel Display

This thesis presents a front-end design of a Scaler chip which is used in Flat Panel Display. The logic function verification is also available on the basis of FPGA ground. The first part of this paper is an introduction to the basic principles and functions about the Scaler chip. The following part describes the design of structures for this Scaler chip. In the final part, the process of the logic verification for the Scaler chip is explicitly explained, which consists of proposing a verification scheme, designing a FPGA verification PCB as well as adjusting previous designs according to the verification results. The Scaler chip here is able to enhance the image effect of visible image signals through an interior image-enhancing module in addition to basic functions like zoomming and shrinking the visibility of signals. The central part of the Scaler is a scaling engine that makes use of bilinear interpolation. It performs arithmetic interpolation operations with data of images and therefore adapts the visibility of the images. In this process, the interpolation coefficients are obtained by referring to corresponding tables in order to reduce the complexities and areas of the chip. Also, in relation to the characteristic of visible image transport, the mentioned scaling engine uses dependent structures with zooming/shrinking in both horizontal and vertical directions. Apart from the above two modules Scaler chip also includes some auxiliary parts such as the Display Timing Generator module and the microprocessor I/O module. FPGA synthesis is employed to perform the logic verification for the front-end design of the Scaler. Concerning the complexity of verification for the Scaler chip's operating at high frequencies, many problems about the setup of the verifying environment need careful treatment. In fact, the focus of this paper is the logic verification of the Scaler chip. The front-end design of the Scaler is firstly described by the Verilog Hardware Description Language and then simulated in logical functions. The results from FPGA verification show that the front-end design here satisfies the expected requirements in related qualities.