Parameter Extraction Techniques And Hardware Implementation For Digital Predistortion

In recent years, with the rapid development of wireless communication, the number of wireless communication users increased sharply, so the spectrum becomes more precious. The modulation techniques such as QAM, QPSK and OFDM are widely used in 3G, LTE and 4G system, linear modulation techniques and multi-carrier modulation techniques is applied with high peak and average ratio of signal, which requires the power amplifier to be designed high efficiency and high linearity. Among the various linearization techniques, digital baseband predistortion is one of the most promising and cost-effective linearization techniques due to its digital implementation that offers significant accuracy and flexibility.After studying the least mean square (LMS), recursive least squares algorithm (RLS), singular value decomposition (SVD) algorithm and the QR-RLS algorithm, the author presents a new method based on QR-RLS systolic array to extract the digital predistortion parameters. Firstly, the thesis discusses nonlinear power amplifier and digital predistortion linearization techniques. After that, the basic principles and implementation of the traditional systolic array and improved systolic array are described in detail. Then through the time delay effect estimate and the adjustment of the platform, there by it can increase the accuracy of the algorithm. The FPGA development board used in this paper is Altera's Stratix2 DSP board. The experimental platform used in the predistortion parameter extraction technique compos of many types of equipment, such as Agilent's Spectrum Analyzer (PSD E4445A) and Vector Signal Generator (VSG, Agilent E4438C).The two-carrier WCDMA signals and three-carrier CDMA2000 signals are selected as the test signals. The program has been debugged and compiled by Nios 2 successfully. After that the extracted parameters are put into the predistortion to confirm the predistortion effect.Test results show that implementation of the designed digital predistortion parameter extraction algorithm can reduce the IMD3 and IMD5 about 15dB, and the performance is stable. It also makes the foundation for realizing the next whole predistortion system.