Research And Design Of Application Specific Instruction Set Processor For Commercial Cryptography Algorithm

As the cornerstone and plank of network information security,cryptology has shown a more and more crucial role in the national security strategy.In this century,China continues to build its own modern cryptographic system,publishes commercial cryptography algorithms and encourages their researches,developments,transformations and applications.However,with the increasing diversity and complexity of security scenarios,higher requirements are put forward for the real-time performance,security and flexibility of cryptography algorithms.In regard to general security scenarios,an ASIP architecture fit with cryptography algorithm is proposed,based on the statistical analysis of the typical characteristics of prevalent cryptography algorithms,which focuses on their performance bottlenecks during data scheduling and status updating.Under this architecture,this thesis implements commercial cryptography algorithms in ASIC and passes its simulation verification.The main contents and characteristics of this thesis are as follows:1.Introduction to the principle,structure and types of commercial cryptography algorithms.Furthermore,via statistical analysis of major cryptography algorithms,the typical characteristics of cryptography algorithm in structure,data and operation are summarized.2.Based on the analysis of the data characteristics of the cryptography algorithms,a programming model of feedback shift register block is proposed.With a view to the data flow in cryptographic algorithm process,the programming model integrates cryptography data access and register iterative updating and establishes their corresponding relationships,simplifying register logic as well as promoting processing performance and increaseing code density with good scalability.3.Based on the analysis of the structural characteristics of the cryptography algorithms,a processor architecture that focuses on iteration is constructed.The execution stage is partitioned into interior and exterior iteration structures,organizing the algorithm data well in the process of input and output.Moreover,considering the difference in the nature and function of operands,interior iteration unit is partitioned into main iteration and accessory iteration parallelly and mapped onto feedback shift registers.On the other hand,the operation processing module is subdivided in line with the operation and data flow to optimize the computation order,so as to realize iterative processing of algorithm parallelly and efficiently.4.Based on the above architecture,a high compressive instruction set with 32-bit/16-bit mixed coding format is proposed in order to improve the instruction density.To take advantage of the free coding of register number index,the iterative instruction and data access instruction are coded synergetically to improve the coherence of data flow,as well as the main iterative instruction and accessory iterative instruction are coded parallelly and make algorithm configuration and instruction operation more flexible.Attributes of instruction coding are settled in terms of data characteristic statistics of the cryptography algorithms to maximize coding width and support more cryptography algorithms.5.Realization and implementation of the proposed ASIP with TSMC 28nm process.It takes compact layout of 42479 ?m2,or approximately 101k equivalent gates.Under the work frequency of 1.5 GHz,the proposed ASIP can achieve throughput of 11.13Gbps,9.6Gbps and 4.8Gbps respectively for SM3,SM4 and ZUC algorithms,indicating that it can meet the requirements of flexibility and high real-time performance.