Studies On Tree Vector Decompressor To Reduce Test Data Volume

In order to ensure the quality of IC products, testing is an essential link. However, the increasing complexity of the circuit under test and a high degree of integration makes it increasingly difficult to test, and makes it cost higer and higer. By adding hardware or changing the circuit structure, to make the designed circuit easy, that means designed for testability. Full-scan test is one of the most effective and popular design for testability technologies. Full-scan test technology changes the sequential circuit testing problem into the combinational circuit test problems, reducing the complexity of test generation and the same time, increasing the coverage of faults. However, the application time, data volume and power consumption of the test are greatly increased.At present, many methods have been proposed to reduce the cost of scan test. BAST technology has been proposed to reduce test stimuli data volume and test application time. The test structure using pseudo-random test generation and Multiple-Input Signnature Register (MISR), that reduces the test stimuli data volume saved in the storage resources ATE. In addition, BAST scan structure contains inverter block, decoding block, and X-masking block. Inverter block in which the role of inversion is to solve the pseudo-random test generation and automatic test pattern generator (ATPG) generated test vectors in a conflict between the care bits. The structure compared with other core structure, is simpler to address compatibility issues. When the ATPG generated test vectors contain more care bits, BAST generated pseudo-random test vectors and ATPG conflict may have more spaces need to invert. It needs one test cycle to invert one bit. Thus test data increases with the test cycle increasing will inevitably reduce the compression ratio. In addition, by using pseudo-random test generation, BAST is difficult to reduce power consumption during test application.This theis designs a tree decompressor to overcome the shortcomings of BAST. The decompressor only XOR gate, and complete binary tree form, reducing the storage of data in the ATE and the need for the external test pins, so as to achieve the objective of reducing the cost of testing. In addition, in the proposed decompressor, its small number outputs are determined by most of its inputs. And the confirmed relationship between the structure and its'outputs is similar to the distribution probability of care bits in scan chains. This method reduces the frequency of the need to flip and the test data volume.Against the structure proposed in this thesis to adapt the algorithm of the method used to solve the equation of ATPG test vectors for encoding the solution as far as possible, so that the decompressor output and ATPG test vectors are not identified in the conflict bit. If the matching process, one of ATPG test vectors can not be solution, then the algorithm will choose a best solution, so that the results obtained with the ATPG test vectors in the positioning of the conflict is indeed at least, thus reducing the testing cycle required number to further reduce test application time and reduce test data volume.Experiments confirmed that for ISCAS'89 benchmark circuits, our prposed approach effectively reduces test data volume keeping high the fault coverag in a little hardware overhead.