Research On Analog Front-End And ADC Circuit Of PXI Based Oscilloscope

With the rapid development and mature application of Computer Science Technology, Test and measurement equipment has also been greatly enhanced in both the functionality and performance. As has been fully integrated with a common computer resources and test and measurement equipment features, card plug-in instrument are also being extensively studied, design and application. PXI-based digital oscilloscope is also a member of the most important of card plug-in instrument.PXI-based digital oscilloscope design is divided into two pieces of software design and hardware design. Hardware design is divided into Conditioning channels and triggering circuit design, High-Speed Data Acquisition System design, High-Speed Memory System Design, PXI Interface Circuit Design four parts. In this paper, Based on ADC plus FPGA framework, wei designed the core of the hardware design of a digital oscilloscope PXI(the high-speed data acquisition circuit and the conditioning channel circuit), And designed high-speed oscilloscope trigger system circuit.Conditioning channel is the key of digital oscilloscope analog design. Through the low-noise FET amplifier and broadband high-speed high-resolution numerical DAC, we realize the continuously adjustable vertical offset. In combination of digital controled attenuator and differential amplifier, we can configure the attenuation network and the Amplifier Network of conditioning channel flexibly and bridge the differential interface between conditioning channel and ADC.In the realization of the trigger system, We have applied high-speed comparator, sophisticated digital potentiometer and so on, to achieve the high quality edge-triggered synchronous signal output and the user configurable Hysteresis trigger and window trigger.In the high-speed data acquisition circuit design, we use the parallel alternating sampling technology to achieve the 2Gsps maximum sampling rate by driving two ADC worke alternately with a high-speed differential clock. In interfacing ADC and FPGA, we designed LVDS receiver to receive and deserialization the high-speed LVDS signal. By fine tuning the phase between clock and data of LVDS receiver, we can get satisfying waveform.