Research And Design Of Gigabit-Capable Pon User Termination

Access network provides a bridge for users to access metropolitan area network andbackbone network, and is the "last mile"of the information transmission channel. In recent years,with the rapid emergence of new service requirements, access network technology began toreceive extensive attention. In the field of wireline access technologies, GPON uses GenericFraming Protocol to package and map Ethernet, TDM, ATM and other businesses and it hasmany features like high-bandwidth, high-speed, efficient transmission and flexible accessing.GPON is considered an ideal technology for broadband access network business and integrativereconstructing by most telecommunication operators.First, this paper introduces the passive optical network technology and its trend ofdevelopment, analyzes the advantages of GPON in relation to other passive optical networktechnologies, and points out its prospect. Then it analyzes the structures of the GPON system andprotocol model, and discusses the key technologies of the layer of GTC.This paper mainly designs GPON user terminals. Based on the analysis of user terminalmodel, it adopts the idea of hierarchical design and proposes an ONU hardware solution whichtakes FPGA as the processing core of layer GTC and embedded microprocessor as the core ofmanagement layer. By analyzing existing products in the market, the paper chooses properphotoelectric transform module, Ethernet controller, and outer interface circuit of FPGA andARM. By studying the information of the chip and the design, the paper designs principlediagrams of the function modules in Cadence OrCAD. At last, it accomplishes the overallprogram design of the circuit.Layer GTC is the core of the GPON system, and the layer of TC based on generic framingprotocol can package a variety of business. This paper studies the TC-layer protocol and theTC-layer frame structure, and focused on the framing sub-layer it puts forwards a modularizedplan. In Quartus II, it achieves FPGA implementation and the overall simulation of the framingsub-layer by using Verilog HDL and Arria GX EP1AGX60DF780C6 as the target device. Finally, the work of this paper is summarized.