Research On Dynamic Routing For Network On Chip With QoS Guarantees

As technology scales down, the design of System-on-Chip encounters some difficult problems: the communication ability can not satisfy the need of system, the overall synchronous clock system is difficult to design, et al. Those problems restrict the scale of IP cores integrated on a sigle chip. Network on chip which based on GALS and packet switching could solve the problems SoC design encounted. Research on routing algorithm is an important branch of NoC research. This article focuses on the research of dynamic routing algorithm for NoC with Quality-of-Service gruarantees, so that it could adjust routing path according to the change of global network states to resolve the problem of network with congestion and failed links.Frist, we analyze QoS requirements and design a group of performance constraints for NoC routing algorithm. On this basis, we propose a dynamic routing algorithm for specific application. In order to evaluate the performance of the routing algorithm, we design NoC model and the routing algorithm with C language.Then, we simulate the routing algorithm in different communication tasks model to evaluate the distribution of network load. After that, we design the routing algorithm with Verilog HDL, and connect it with NoC system model of our group to evaluate the design. On this basis, we simulate the routing algorithm in different network status and network load to acquire QoS metrics. Then we compare them with XY routing and DyXY routing to analyze the performance of the algorithm. Finally, we synthesize the algorithm on EDA platform of Synopsys to analyze area and power cost.By comparing and analyzing the QoS metrics we obtained from RTL-level simulation, the results indicate that the routing algorithm proposed in this paper could balance the network load effectively. Thereby, packet congestion probability is reduced and the performance of the network with congestion and failed links is improved.