Research And Design On VLSI Architecture Supporting MBAFF Motion Estimation Engine

With the development of the Internet and 3G mobile communications technology, the transmission and processing of digital video has become the hot technology currently. The key technology of which is how to improve the effect of digital video compression. There is great improvement in the current level of video compression in theory with the proposition of H.264/AVC video compression coding standard, which is been regarded as a new generation standard. The hardware implementation of the algorithm has been completed by VLSI, and the algorithm can be efficiently used in various fields.In H.264/AVC standard, 1/4 pixel resolution motion estimation algorithm, adaptive block size and frame field adaptive coding are supported. These greatly increase the computing complexity of motion estimation; this paper puts forward on VLSI Architecture Supporting MBAFF Motion Estimation Engine. Through innovative parallel module structure and high-efficiency SAD matching operation unit, we can obtain SAD results in different block size and coding mode by only one SAD matching computation. Optimal block segmentation and frame field mode decision can be obtained by analyzing the results.After comprehensive analysis of this design, the result shows that, in the worst case, motion compensation of one macroblock can be finished in 1109 clock cycles in this design with the frequency 150MHz. Thus, the proposed architecture can achieve a high performance of mode decision for macroblock coding, and can be used for high-resolution, real-time video coding.