A Method For Designing Fault-tolerable Network On Chips Based On FPGA

With the development of the very large scale integrated circuit, the number of transistors integrated on a single chip is more and more, so the hundreds of IP cores can be integrated on a chip. As the traditional System on Chip (SoC) using a bus structure, SoC has the problems such as the limited address space, only supported the communication of a pair of user at the same time, the synchronization of global clock and so on. As the number of cores increasing, these issues will become more serious. Therefore, SoC will not adapt to the development of integrated circuits in the future. In order to solve these problems, Network on Chip (NoC), a new interconnected architecture, is proposed by some experts, who draw on the computer network technology. NoC could solve the problems in traditional SoC, and use the communication mechanism of Globally Asynchronous Locally Synchronous (GALS), and provide the good parallel communication capabilities. So NoC become the new architecture for the process of nanotechnology.However,with the scale of integrated circuits entering into nanometer form in the expansion,because of reducing quickly for work voltage and hoisting quickly for frequency of work,circuits are more susceptive to particle's radiating,yawp from power supply or interlinkage and electromagnetism's disturbing.As a result, soft error rate arosed by instantaneous fault climbing up quickly.Some correlative documents forecast that soft error rate will climb up to 9 at the order of magnitude.Therefore,correcting soft error has been one of the key factors through NoC'design.On the other hand,with the technics dimension of manufacture minishing,the operating rate of single silicon and the density of a single silicon advances further.However,with feature size of silicon accessing atomic level,VLSI(very large scale integrated circuit) is being more dissimilar and weak. Intending VLSI design will be composed with billons of transistors.more than 10 percent of these transistors will generate hardware faults due to fray and windage of technics.Therefore,designing NoC must take potential hardware faults into account.Stochastic soft errors and potential hardware faults are the key issues during the stage of NoC design.The main work is as follows: (1) Introduced the background ,the key issues and international research actuality of NoC. Moreover,we also introduced normal hardware structure of NoC and the design flow based FPGA.(2)Lucubrated hardware structure of RNI.We advanced a sort of RNI structure,which can handle soft error.This scheme add coding circuit to generate parity bit and add decoding circuit to correct one bit of soft error.Compared with other RNI,this structure has characteristic of better reliability and lower hardware spending.Experiment result shows that our design passed function simulation,and had the characteristic of lower hardware spending.(3)Lucubrated router structure of NoC. We add a code circuit to generate parity bit and a decoding circuit to correct a bit of software error in the resource network interface circuit.We also set a BIST circuit in the standard router and add some flag registers in a RC module which can decide whether the adjacent router is broken-down or not.If the next hop router is fault-free for the transferred data, the data will be forworded by the original port, otherwise, the data will be forwarded by another port.The proposed method can make the router hardware fault avoided.Compared to other NoC groupwares, the experiments show that the structure we proposed has high reliability and low-overhead for the resource-network interface.We also can reuse partial modules of the standard routers.Through the functional simulation, we can achieve a smaller hardware overhead.