Research And Implementation Of Synchronization Module For PolSK-OCDM System

Polarization Shift Keying Optical Code Division Multiplexing (PolSK-OCDM) system,which is based on the polarization decoding, is a new type of OCDM systems. It has a series of advantages compared to the traditional structures. This paper analyzes the characteristic of PolSK-OCDM system and especially solves the problem of PN code synchronization by FPGA.In ChapterⅠ, it firstly introduces the principle, classification, application and the history of OCDM system. Then the author describes PolSK-OCDM system and the differences between this system and other traditional systems.At the same time, it specially gives the problem and solution of PN code synchronization.In chapterⅡ, it mainly discusses the theory of synchronization. First, the synchronization plan of PolSK-OCDM system is proposed. Second, the selection principle of address code and the properties of m sequence are discussed. Third, it focuses on the theoretical knowledge of PN code synchronization, especially analyzes and compares the algorithm of the PN code acquisition and PN code tracking, which provides a theoretical basis for logic design.ChapterⅢis the key part of this paper. It analyzes the process and results of logic design in detail for the synchronization module. First it introduces some basic knowledge of logic design, including the parameters of XC3S400, the information of hardware and software platforms and so on. Then the specification and the requirements for the design are proposed. At the same time, the design idea, the key code, the circuit connection and the simulation results of logic design are described in detail. This plan of logic design, which based on top-down and modular principle, is developed by Verilog HDL, using algorithm of matched filter and delay locked loop. Finally, it introduces the hardware testing process and proves the success of the synchronization module with the chip rate of 19.44Mbit/s and the accuracy of 1/4 chip.In ChapterⅣ, it introduces some experiences and skills of logic design based on FPGA and gives some advice to improve the future work.