Design & Implementation Of An Ethernet Interface For Point-to-point Transimission Based On FPGA

Backend transmission has always been a bottleneck for the design of real-time monitoring system. Fast development of modern computer network technology represented by fast Ethernet technology has brought a new technical reformation to real-time transmission. However, real-time transmission of data in abundance would tend to be unavailable if there were no general computer. Embedded Ethernet IP cores provided by chip plants can only function on high-end FPGA, thus leading to high cost of implementation and difficulty in acquiring wide application.Considering such issues mentioned above, a plan of embedded gigabit Ethernet interface is proposed in the thesis to seek a breakthrough for the real-time point-point transmission of data in abundance. Based on detailed analysis of TCP/IP protocol, an overall hardware design scheme of the Ethernet interface is presented, with the emphasis on the implementation of Data Encapsulation Module, the top-drawer part of the design. Based on the study on the message formats of UDP and IP from TCP/IP protocol and the MAC frame structure prescribed in IEEE802.3 protocol, it is made a creative strategy of MAC frame header encapsulation together with UDP and IP header, while apart from MAC frame footer, thus improving the level of resource utilization and reducing the design complexity. Data encapsulation has been accomplished before bit conversion of the MAC frame is executed to meet the requirements of GMII interface prescribed by the gigabit Ethernet PHY chip.With Quartus II as its design platform and Verilog HDL as its development language, the gigabit Ethernet interface is implemented on the FPGA chip EP2C35F672C6 from Altera. Simulation results reveal that the design has realized the continuous real-time transmission of data in abundance, met the requirement of gigabit Ethernet, and achieved expecting performance.