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DFM For Post-CMP Planarity In VLSI Back-End Design

Posted on:2011-11-29Degree:MasterType:Thesis
Country:ChinaCandidate:Y H ZhangFull Text:PDF
GTID:2178330332961298Subject:Physical Electronics
Abstract/Summary:PDF Full Text Request
For almost half a century, the IC industry, following the "Moore's Law", develop rapidly. The integration density of transistors on IC doubles every 18 months, and correspondingly, the device feature size shrinks by 0.7 times synchronously. Advanced technology node has reached 65nm,45nm, and even 32nm,23nm. However, with the continued aggressive scaling down of feature size, there are more and more manufacturing variations that affect parametric yield in processing technique, and as technology node has reached 65nm,45nm and even below, the influence degree of various defects on parametric yield is markedly outstanding.An ideal planarization of chip surface topography is a prerequisite for lithography,and the chemical mechanical polishing (CMP) technology is a effective process means to flatten the wafer surface. However, with the continued aggressive scaling down of technology node, CMP process faces enormous challenges. In the dual damascene process, because of the uneven distribution of metal density, and the different hardness of metal Cu, diffusion barrier layer and dielectric, the post-CMP wafer surface occurs dishing defect and erosion defect. These defects not only bring DOF problem for litho, and also affect the wire's RC parameters seriously, which will damage the parametric yield and performance of IC seriously. The DFM technique is a bridge between IC design and manufacturing processes, which aim to improve both functional and parametric yield through layout optimization in VLSI back-end design.To avoid post-CMP defects, a DFM solution, dummy metal fill, has been posed. Among so many fill methods, the model-based dummy fill is becoming a trend recently, however, this method is time-consuming, and occupy much resources. So, we make an improvement on the traditional rule-based dummy fill method and has conducted the experimental verification. In our experiment, we fill the routed layout using improved rule-based fill method and model-based fill method separately, and through the contrastive analysis of simulation result we can draw the conclusion that:the planarization effect of improved rule-based fill method is still remarkable in nanometer process, and is not inferior to that of model-based fill method.
Keywords/Search Tags:Integrated Circuit (IC), Design for manufacturability(DFM), Production yield, Chemical mechanical polishing(CMP), Planarity, Dummy metal fill
PDF Full Text Request
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