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The Research And FPGA Implementation Of Pseudo-code Acquisition Method Based On Iterative Detection

Posted on:2011-02-10Degree:MasterType:Thesis
Country:ChinaCandidate:N K ZongFull Text:PDF
GTID:2178330332960543Subject:Navigation, guidance and control
Abstract/Summary:PDF Full Text Request
It's very important to realize rapid acquisition of long pseudo-code (PN code) in spread spectrum communications. However, there are some problems in traditional acquisition methods. On the one hand, the PN code phase needs to be searched in a large scope, and this will lead a long acquisition time, as a result, the rapid acquisition can not be realized; on the other hand, the computation complexity of existing rapid acquisition method is too complexity to be realized by hardware or software. So, it's desire to find a rapid PN code acquisition method with low complexity, and consequently, one acquisition method based on iterative detection is researched in this paper, and its FPGA implementation is also given.In the paper, the mathematic model about iterative acquisition is set up based on iterative detection theory. To further improve the performance of iterative acquisition algorithm, an iterative PN code acquisition method based on information optimization is proposed in the paper, which can improves the quality of the initial soft information by using multiple samples per chip. However, the improvement will be affected seriously by the timing error and carrier phase offset. To solve both of these problems, a new Maximum-Likelihood (ML) estimation with low complexity is introduced to mitigate the timing error, and a phase search method is introduced to mitigate the carrier phase offset. What's more, to reduce the complexity of the algorithms, a low complexity iterative acquisition method is proposed in the paper on the analyses of its complexity. Proposed methods can both reduce the time and the space complexity of the primary algorithm. Finally, the performance analyses method of iterative acquisition is set up by mathematic analyses. The analyses and the computer simulations have proved that proposed method could realize rapid PN code acquisition at low signal-to-noise ratio(SNR) with low complexity.The FPGA architecture of proposed PN code acquisition algorithm is given in the paper based on theoretic analysis. Specifically, detailed designs, implementations and testing of each module are given in the paper. In the design, the control path and the data path of the architecture are designed separately whose thought is generated from the algorithm state machine (ASM). Finally, an integration of each module is formed; and the testing results show that the implementation of PN code acquisition algorithms based on iterative detection can realize rapid PN code acquisition at low SNR with low complexity.
Keywords/Search Tags:PN Code Acquisition, Iterative Detection, Information Optimization, Low Complexity, FPGA Implementation
PDF Full Text Request
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