FPGA Implementation Of Complex-Rotary Encoder And Decoder Based On Iterative Mechanism

Channel encoding and decoding are very important in digital communication system since their performance determine the goodness of whole communication system. Simple, reliable and low-redundant coding methods are explored by many scholars for a long time, especially in the applications of high capacity storage and high speed data transmissions.The main motivation of complex-rotary (CR) code was to deal with the complexity issue in error-control techniques for correcting multiple errors. In recent research, especially the introduction of iterative decoding method, it has been shown that the CR codes have not only low implementation complexity, but also high decoding performance in terms of bit error rate (BER), thus becoming a very promising coding candidate in practical applications.In this thesis, a high code-rate (47, 13) complex-rotary encoder and decoder are designed using FPGA. A decoding algorithm with maximum four iterations is implemented on an ALTERA development board. Test results demonstrate that the decoder operates stably and correctly.There are six chapters in this thesis. Chapter 1 introduces the background, related research and hardware platform of complex-rotary code. Chapter 2 presents the basic principle of complex-rotary encoding and decoding, the improved iterative majority decoding algorithms, together with their c-programming based simulation and performance analysis. Chapter 3 describes in details the design of FPGA encoder, such as the pins and hardware structure, internal and external signal and their design procedure. Chapter 4 describes the design of FPGA decoder, including pins and hardware structure, internal and external signal, their design procedure and the implementation of iterative decoder. Chapter 5 analyses the performance of FPGA decoder and presents a hardware simulation method based on ALTERA development board. Then the hardware simulation result is compared with that of the corresponding high-level software simulation, demonstrating the corretness and effectiveness of the hardware design. Next, the simulation result of complex-rotary decoder is also compared with a RS decoder with the same code-rate, resulting a basis for future potential applications. In the last chapter, the author summarizes the thesis, analyses some problems encountered, and gives some suggestions for further improvements.