Research On Uplink Receiver Of SCMA And Its FPGA Implementation

The 5th Generation of Mobile Communication(5G)has placed higher requirements on air interface technology,the traditional orthogonal multiple access reduces the complexity of the receiver by allocating orthogonal resources to each user,which will obviously limit the amount of access devices with the increasingly scarce spectrum resources.In order to meet future communication better,non-orthogonal multiple access(NOMA)has become the best air interface technology for 5G,and SCMA is one of them.SCMA can effectively improve spectrum utilization and increase the number of user connections with the help of sparse codebooks.For the commercialization of SCMA technology,it is of practical application value to study the hardware implementation of SCMA.Therefore,this thesis conducts research on SCMA uplink receiver,exploring detection algorithm suitable for FPGA implementation.The main research contents are as follows:This thsis starts with designing a low complexity detecting algorithm for SCMA receiver.To reduce the complexity of the traditional MPA,DFG-MPA and MaclaurinLOG-MPA are put forward as solution,from the perspective of mathematical derivation and reducing nodes participating iteration.Nodes can be eliminated from iteration in advance by setting reasonable threshold in DFG-MPA,which can reduce decoding complexity while maintain good performance.Simulation result shows,when the threshold is set to 0.3,the BER performance of DFG-MPA is similar to that of the traditional MPA which maximum iterations is 3,while the average iterations of former is less than 3.Macluarin-LOG-MPA uses Maclaurin series to eliminate nonlinear calculation based on LOG-MPA,it performs nearly as better as LOG-MPA,and 0.5 d B better than MAX-LOGMPA with worst performance,while its complexity is lower.Then it is proved through simulation that the three algorithms can still keep good performance under the condition of parallel computing.Furthermore,combining advantages of the two algorithms,a message detection scheme suitable for FPGA implementation is proposed,which reduces the decoding complecity,while floating-point simulation result shows no significant performance degradation.Finally,Based on fixed-point simulation results of proposed message passing algorithm,this thesis proposes an FPGA implementation architecture that reduces decoding delay and hardware resource occupation,improving storage structure,to enhance data reading and caculating efficiency.According to the hardware architecture,the receiver hardware circuit is implemented using Verilog,and Modelsim simulation shows that the function and timing of the design is correct.The systhesize report indicates that,comparing with the traditional receiver scheme,scheme of the thesis has no significant increase in resource occupation rate,while maximum frequency of the design can reach about 220 MHz,and system throughout increase significantly.Meanwhile,the tests show that the BER performance of FPGA system is basically consistent with the fixed-point simulation results,meeting the design requirements.