Research Of Implementation Method About Multi-core Cache Consistency On The On-Chip Network

Due to the continuous development of the semiconductor technology makes the processor of SOC number increasing, the traditional bus or point-to-point communication structure begin to appear the power consumption, delay and bandwidth, scalability and other issues, as well as global clock synchronization is difficult, address space is limited, unable to support the communication of multi core parallel. In order to solve these problems, there is a need for a new method of communication between the multi-core processor. Network on chip emerge as the times require, and it is a new communication method. System on chip, its main idea is the application of computer network technology in IC design, in order to solve the communication problem of interconnection between multi-core systems. Because of the demand of parallel programming, cache coherence problem must be considered. Taking aim at NOC cache coherence protocol, analysis NOC consistent key problem in detail and deeply.This paper first analysis the advantages of multi-core on chip network, and further research NOC cache consistency problem, analysis the NOC multi-core cache consistency related knowledge.Introduct NOC architecture, topology structure, flow control mechanism and routing structure and routing algorithms and cache replacement algorithm,cache write strategy, snooping protocols, directory protocols and NOC cache coherence characteristics. Based on MESI protocols and directory protocol, put forward a new NOC cache coherence protocol. Shared memory in each data block has a directory, recording copy status of data blocks in the nucleus. Each processor has a cache controller, used to record the status of cache, as well as to read and write cache processing. Focuses on NOC cache consistency communication problems, propose a broadcast routing mechanism which realizing the master node broadcasts cache invalid data packet to the destination node and arbitral priority routing for competing the shared memory. Try to reduce the delay, ensure the coherence of cache. Finally introduct the data packet format, network interface between IP and NoC and router overall structure in detail.In the software platform, combine with the classical virtual channel routing mechanism and the NOC cache coherence protocol, build the communication architecture of IP, NI, and router. Use Verilog HDL language to write code to achieve the NOC architecture, cache and shared memory RAM. Using modelsim10.1d as simulation tool to realize the proposed NOC cache coherence protocol, and evaluating its performance.