The Research Of Filed Programmable Gate Array On Modeling Method

Technology mapping can also be called "library unit binding", which is a very important part in the process of ultra large scale integrated circuit design. The target of technology mapping is that using a specific method to make a set of Boolean logic functions network expressed in a specific library unit. In the other words, it is to connect units(elements) in the actual process libraries to achieve the desired logic functions. Technology mapping provides a design approach which makes the logic functions circuits expressed with the physic structure, and it bridges the gap between the actual process technology and logic functions design.In the method of library based technology mapping, the quality of chip model determines the quality of technology mapping and the CAD tools to implement the users' design. With the FPGA's( Field-Programmable Gate Array)continuing improvement at function, density and performance, the FPGA's structure becomes more complex and larger, which requires a simple and efficient method of devices construction process to adapt to the changing structure of FPGA chips. Therefore, it's imperative to construct a low-level FPGA chip model with high reusability to improve speed of the CAD tool. At the same time, separating the CAD tool's software layer and physical layer to improve its versatility is also an important part of technology mapping.In order to solve the problems above, this paper makes a discussion and analysis in detail with the basic principles and processes of technology mapping , and does the following works based on it: 1) After analysis of advantages and disadvantages of existing technology mapping algorithm, a new FPGA technology mapping algorithm based on architercture library has been proposed;2) After analysis of the structure and function of island-shaped and hierarchical-shaped chips, a new hardware description language Veric that compatibled with the features of VHDL, C + + and Perl language has been proposed;3) Using Veric language constructs model of XCV100 chip that of Virtex series: building architecture model by freach loop and positioning statements; building functional model by inheritance approach , while achieving the technology mapping ;4)Veric compiler and C + + class is introduced, therefore makes the physical architecture and software separated, so enhances the versatility of CAD tool; 5) In experiment, LVS module of Cadence tool and Modelsim tool are used to simulate the architecture and function of the model, the results prove that it's correct.In practice the CAD tool's synthesis functions can operate correctly.