Research On Bus Coding Schemes And FPGA Verification

Deep-submicron buses suffer from many problems like power consumption, crosstalk delay and noise. Through low power coding, crosstalk avoidance coding and error control coding techniques, these problems can be effectively solved to improve bus performance and reliability. At present, the research focus on the unified bus coding scheme to simultaneously solve power, delay and reliability. In addition, the effective verification and hardware implementation of bus coding scheme require further study.Based on the characteristics and development trend of bus coding techniques, a novel adaptive spatio-temporal encoding (ASTE) was proposed in this thesis. Improved segmental bus-invert coding, adaptive temporal coding and error detecting circuit are designed to reduce power, crosstalk and noise respectively.Based on the traditional verification methods, a preliminary study was provided on FPGA verification platform targeting bus coding system. Three unified coding schemes described in the thesis were evaluated by FPGA verification for different bus data. Results indicate that ASTE reduces 6.8%-14% power over other two schemes and saves about 42% time over the uncoded method with small overhead, thus outweighing other schemes on the whole.