Crosstalk Avoidance Coding For Low Power Bus And FPGA Verification

With the shrinking of Integrated Circuits feature sizes, the length of globalwire and the frequency of the clock continue to increase, meanwhile the interval ofthe wires shrinks rapidly, all these factors contribute to the deterioration of the wireperformance. In deep sub-micron process, the value of coupling capacitance hasbeen close to or exceeding self capacitance. Bus energy consumption has alreadyoccupied20%-30%of the total power consumption, becomes the key factor toimprove chip performance. Bus coding, a kind of algorithm level optimizationmethod, will not be influenced by process and electrical parameters, so it has abroad application in low power consumption, crosstalk avoidance, error detectionand correction. Bus coding has incomparable advantages than traditional methods inimproving the bus performance.This paper, based on the space-time bus coding method, proposes a new kindof low power consumption and crosstalk avoidance bus coding algorithm.Space-time bus coding has several advantages such as less flag wires, faster spatialencoding speed, etc. The first step of the new algorithm is to divide the bus intocertain groups in order to reduce the possibility of malignant crosstalk occurrence,then it focus on encoding sub-bus in each group respectively. Code can get the resttwo kinds of data sources based on the input data, check with the bus datarespectively to find out whether there is a malignant crosstalk, and finally select theideal data type to transfer on the bus; For the worst crosstalk mode, we should sendthe block word at the negedge of the clock to eliminate malignant crosstalk beforesending the valid data. To make sure decoder decode correctly, redundancy line willsend the selected data type.Based on the deep sub-micron bus model, simulation result by MATLABshows that the power consumption, for32-bit random data, could be reduced byabout24.9%, and the occurrence rate of worst crosstalk can be reduced to11%. Inaddition, to analyze the power consumption of coding system, the PrimePowersoftware get the gate level power consumption of the encoder, decoder, and the busat work. Under the180nm process and about9.6mm bus, the new coding algorithm, compared to the unencoded bus system, can save about15.34%of system powerconsumption, and the effect would be much more obvious with the increase of thebus length and reduce of the feature size. To analyze the effects of the code at powerconsumption and crosstalk avoidance, the power and delay information are obtainedafter downloading the code to FPGA. The result shows that bus coding can reducethe power consumption of bus and the delay for the reason of crosstalk. In addition,The waveform can be much better compared to the system without bus coding. In aword, the new bus coding algorithm can achieve the goal of reducing bus powerconsumption and transferring delay for crosstalk.