A Low-Power High-Precision Audio DAC

The prosperous development and wide application of digital audio technology during the first decade of this century has promoted the research and development of audio DAC in China. In the contex of low-carbon energy, the problem of power consumption becomes particularly conspicuous in portable electronic products, which desire the extention of usage time. Meanwhile, human ears are very sensitive to subtle noise, so 16-bit to-24 bit DACs are extensively adopted in order to aquire better sound quality. Therefore, the research and development on low-power, high-resolution audio DAC is extremely important in meeting the needs of market and in the enhancement of IC industry competitiveness of our country.In this context, this dissertation designed and implemented a low-power, high-precision audio DAC and complete the whole design process from the specification definition to tapeout and chip measurement.The main work and innovations include:1. Summarized D/A conversion technology, performed system-level analysis in the adopted∑-Δstrucuture and determined the overall structure, then deeply discussed the operation principles and design key points of all the modules in the analog part, summarized the principles and experience on how to understand the fabrication process and how to draw the layout, and finally designed a low-power, high-precision audio DAC. There are discussions about several problems in mixed-signal IC design among these chapters, such as the level matching, the inference supression between digital part and analog part, the mixed-signal simulation and layout verification, and so on.2. This design is implemented in SMIC 0.18μm Mixed-Signal 1P6M CMOS process, the core area is 1.81 mm2. The typical SNDR of analog part is 89 dB, which consumes 19.1 mW, and this number decreases to 9.1 mW without buffers. The typical SNDR of the whole DAC is 84 dB, which consumes 20.3 mW, and this number decreases to 10.3 mW without buffers. Besides, the prototype yield is 90%. The measured resultes achieved our expected goals.3. Performed the design improvement after chip tests and proposed a series of feasible schemes, including high-performance bandgap reference, the generation of on-chip reference voltage and its buffering, low threshold voltage CMOS switch, and so forth. Compared to the simulation result of former version, these schemes reduce the power consumption of analog part by 58% and decrease THD by 4 dB, which provided useful reference to future work.