The Research Of H.264 Decoder Based On Software And Hardware Co_design

In 2003, the next-generation video compression standard H.264 is officially announced by the ITU_T/IEC. Compared to previous compression standards, the more high compression ratio and network compatibility is fully reflected in.In the present,the codec chip based on all grades has been market-oriented. The research area,from the initial PC-platform and algorithm optimization, has extended to the current variety of platforms, structure design optimization. The extensive development of the portable market, a number of portable devices have appeared,such as video cameras, wireless video phones and portable terminalsFor such applications, the research of H.264 decoder of the paper is based on platform of Xilinx SOPC. Its design is based on the idea of hardware and software co-design. Its advantage lies in the flexibility of using software processing and speed of using FPGA processing. Microblaze soft core processor within the software part is responsible for the resolution of slice decoder and above parameters. Other high computational complexity of the decoder module design uses FPGA.Firstly, based on the computational complexity of each module of the decoder, the partition of hardware and software of the decoder is obtained. FPGA hardware modules mainly relates to inverse quantization and inverse transform(IQIT) and deblocking filter design optimization.The IQIT module is improved by multiplexing circuit area and reducing the computational complexity.The result shows that it needs 402 clock cycles when processing a MB in the worst condition for 16×16 intra prediction. The highest frequecy is 120MHZ.Four_pipelined structure and optimizated filtering order are used for deblocking filter. Continuity and rapid of filtering process are realized and the high-throughput characteristic is reflected. The experiment shows that only 200 cycles are needed to filter a MB. At 100MHz,the throughput is 500MBs/s.Secondly,the software,hardware platform and H.264 decoder IP core communication interface based on Microblaze OPB bus are designed. Software platform mainly relates to C code porting and optimization and online authentication is done. Partial online authentication of the hardware and decoder interface is aslo done. Theory and experiment show that it can achieve the decoding speed of 76frames/s for CIF video.Finally, the simulation system of LDPC codec for H.264 video transmission is. designed.For the software part,the codec state config is done by NIOS_Ⅱprocessor of Altera and codec modules are done by FPGA. The LDPC codec system can achieves a two-way communication with flexible configuration.