The FPGA Design Of AES Processor On The IC Card

With the carried out of "Golden Card Project" in our country, IC cards are wildly used in our daily lives. IC card is a quite important medium of transmission, storage and exchange of information. So the security measures offered by IC card must guarantee the safety of information. But nowadays, most IC cards still encrypt or decrypt information with DES or T-DES which has been proved to be out-of-date. In 2002, the new encryption standard—AES(advanced encryption standard) was announced by U.S.A.. In these several years, it is implemented in communication and internet. So it becomes urgent now to put AES into encrypting or decrypting information on IC card. And the design of AES processor based on IC card also becomes very important.This thesis introduces the whole architecture and four individual transformations first, and explains the principles of encryption and decryption at length. For the several architectures of the hardware implement of AES, this thesis mainly analyzes and contrasts the characteristics of pipeline architecture, sub-pipelined architecture and loop unrolling architecture. According to the characteristics of information and the requirement for chip area in IC card, the thesis chooses the sub-pipelined architecture as the architecture of AES processor in IC card, and further more, improves the sub-pipelined architecture so that it will be adapted to IC card more. In the aspect of key expansion, synchronous expansion is adopted, which saves the storage area of round keys — when the round operation is in progress, the key expansion unit produces the next round key. On the basis of these measures, the thesis also optimizes the algorithmic, so that the encryption and decryption can share the hardware and the area of AES processor can be saved. The outstanding characteristic of the improved design is making the hardware be shared to the greatest extent, and the occupied area of the hardware can be greatly saved.After the analysis of the architecture of AES processor based on IC card, the thesis adopts a "top-down" design method and describes the whole design with Verilog HDL at the full synthesizable RTL level on Xilinx's ISE6.1. The simulation of AES processor is performed with the results showing that the design can correctly complete encryption and decryption. And then the implement of AES processor is also performed based on the Xilinx's virtex xcv-pq240 FPGA with the results showing that the frequency is 20.032MHz and can meet the real-time requirements for IC card applications.