Special-purpose hardware to support algorithmic-level simulation

The purpose of this research is to explore methods to improve the performance of algorithmic level simulators for digital systems. The approach chosen is to use special-purpose hardware, an algorithmic simulation engine, to reduce the simulation time required.;Then the architecture of the algorithmic simulation engine was evaluated. A set of experiments was used to determine where the performance improvement came from and what features of the simulations affect the performance of the simulation engine. The experiments determined the effects of writing style, instruction mix and architecture on the performance of the algorithmic simulation engine. The algorithmic simulation engine was able to simulate designs 150 to 700 times faster than the ISPS Simulator. From these experiments the successfulness of the architecture was determined along with possible improvements to the architecture.;The two main contributions of this research are a set of requirements for the architecture of an algorithmic simulation engine and an application of these requirements to produce an algorithmic simulation engine for the ISPS language.;First an architecture for an algorithmic simulation engine was developed. To do this, algorithmic level simulators running on several existing architectures were evaluated. The results of these evaluations were used to develop a set of requirements for the architecture of the algorithmic simulation engine, and these requirements were used to guide the design of an algorithmic simulation engine for the ISPS hardware description language. The architecture proposed has two parts, a von Neumann part to evaluate control operations and a dataflow part to evaluate data operations.