The Design And Verification For Memory Management Unit Of 32-bit MIPS Microprocessor

The technilogy of CPU's design and manufacture is the base of IT technology and industry . The work of CPU design is carried through to possess the momentous academic value and realistic value . Memory management is the kernel technology of modern CPU design . It's the key of the CPU efficiency .To increase the embedded processors more, base on the research of characteristics of existing 32-bit MIPS microprocessor and the characteristicsof memory management unit (MMU), the hierarchical data and instrcution integration for Transfer Look-aside Buffer (TLB) is created in this paper. By this design and with the help of bottom-up hierarchical page and Address-Space Identifier (ASID) protection system, the translation from virtual page number ( VPN ) to physical frame number (PFN) can be completed in two periods averagely ,and the CPU efficiency is increased remarkably. The main tasks of this paper are as follows:(1) Carries on the analysis to embedded processors architecture ,and obtain the conclusion the CPU efficiency is increased remarkably by that virtual memory management , the request for virtual memory management technology is analysised . (2) The design for MMU of 32-bit MIPS microprocessor is researched, the design for the page in MMU is discussed, this design modes is obtained: bottom-up hierarchical page , hierarchical data and instrcution integration TLB,and ASID protection system; (3) Design is achievemented by the platform QuartusⅡ5.1, the Verilog hardware descrition language is used to carry on the design description to the MMU. This modules'logical design of the MMU is completed, the detailed exlianation and the discussion is given to the entire design process and the design detail.(4) Alter StratixⅡE P2S130F1024C5 FPGA CHIP is used to do the logic synthesis and place & route. Then the function simulation and timing simulation is maked by the Modelsim tool.The conclusion is that by the design for MMU which obtain the design modes: bottom-up hierarchical page , hierarchical data and instrcution integration TLB, the efficiency from VPV to PFN is increased, and the CPU efficiency is also increased remarkably .