A Research On High Data Rate Satellite Demodulation Algorithm

Modem is one of the key technologies of the data transmission of the satellite system. It is a key especially to spread the system to a high data transmission yards. With the rapid development of the space project of our country, the requirement of real-time transfer data rate from the satellite to the ground is higher and higher. But up till now, the hundreds Mbps Modem has not yet been developed in China. So it makes far-reaching sense to choose the subject as my subject of academic dissertation.In this paper the author has done plenty of research work on demodulation technology, which is back grounded 150 Mbps satellite data transmission. The demodulation technology involves carrier recovery and time synchronization, so that it is the key and difficult factor of the modem and even of the whole data transmission system.This paper contrasts deeply various kinds of modem framework in chapter two, and refers the achievements of the same research field abroad. Taking into account the satellite load limits, such as low power consumption, small cubage, high speed broadband, easy implementation and high reliability, the QPSK modem framework with ripe technology, moderate algorithm complexity and strong anti-interference, is employed. Because of the restriction of digital device speed, presently, it is very difficult to realize all digital demodulations whose transmission speed is as high as 150Mbps.So the parallel receiver technology must be employed. In chapter three the author offers a relatively deep discussion on carrier recovery and time synchronization. Adopt the frequency tracking and phase tracking method to combine together to realize the carrier recovery. The COSTAS loop can anti the Gauss noise, and in the case of the serious shift frequency the frequency tracking circuit can draw the' local carrier into the range of catching of COSTAS loop. As the parallel receiver technology is used, the operational speed of each unit is greatly reduced, consequently the interpolation algorithm can be employed to implement the time synchronization. The time error is calculated directly from sampled value and then the interpolation algorithm can run with the time error. Contrasted with the feedback loop this method is more accurate, the timing error is caught faster, the time resource is not necessary and it does not occupy resources of the hardware in DSP. Therefore it is suitable for the designing requirement of the whole software realization. In chapter four some algorithms discussed in this paper is simulated, and the simulation result is analyzed.