The Research And Implementation Of MPEG-4 Decoding System

With the rapid development in the areas of communication and computer technologies, digital video plays a more and more important role in information society. At the same time the development of Very Large Scale Integrate circuit (VLSI) and Programmable Logic Device (such as FPGA etc.) makes real-time video compression and transportation possible.This dissertation presents the research result of several issues in video decoding and its hardware implementation. Based on studies an MPEG-4 SP video decoding system is proposed. The system is based on FPGA and ARM. Most procedures in MPEG-4 video decoding system are fulfilled by FPGA, and ARM CPU is used to set up the demonstration system. It realizes real-time video decoding when the input picture resolution is 352 X 288 and its frame rate is 25 frames per second and the input bit rate can be up to 4Mbps. The performance of this system is good.