Design Methodology Of Reconfigurable Architecture For MPEG-2/H.264Dual-Standard Video Decoder

Standard diversification for video codecs is prevailing in video signalprocessing area. Data-intensive and real-time video processing makes evensigle-standard video decoder large-scale and complicated digital integratedcircuits. Requirements of multi-standard video decoders enhance the designdifficulties. Accordingly, design methodologies of reconfigurable architectuersfor multi-standard integrated video decoders are studied in this work toimprove the resource usage efficiency of the hardware.Two kinds of design methodologies of reconfigurable architecture formulti-standard video decoders are presented in this paper, respectively. Thefirst one is for established independent decoders with different standards. Adesign example of MPEG-2/H.264dual-standard video decoder is presented, and25%hardware is saved; the PSNR of the reconfigurable decoder is30dB, whichcould meet the primary requirements of applications.The second flow is to design the brand-new multi-standard video decoder insystem level. Also with a design example of MPEG-2/H.264dual-standard videodecoder, a dual-standard video decoder architecture and system-level model arebuilded with SystemC. System analysis data, such as on-chip communicationbalance and algorithm complexity, can be derived from the system model.More, the architecture of the system-level model could be used as a referencefor RTL-level implementation of the reconfigurable video decoder.Compared with the current design methodologies of reconfigurable architecture,the first proposed flow considers reconfiguration for established systems withdefferent architecture, which is not mentioned before, and the seconded onegets faster development with efficient system analysis.