Research On The IP Design Methodology Based On The DSM Technology

With the rapid growth of silicon capability, the technology promises new levels of system integration onto a single chip, normally termed SOC (System on a Chip). Function modularization, as the basic feature of SOC, makes it to be easily updated with new functions and shorten the product time to market, turning into the trend of the future IC industry. However, the gap between design capability and the process technology becomes the obstacle to the development of SOC. IP based design methodology is the most promising opportunity to bridge the gap. At the same time, DSM manufacture issues new problems and challenges to IC design and its design methodology, especially the timing problem. When the silicon technology comes to deep sub-micron level, the interconnect delay exceeds the gate delay; and because of the increase of 1C work frequency, the allowable errors become smaller, and the influence of the transmission delay gets bigger, which increase the difficulty of the circuit design. So the STA (Static Timing Analysis) step and the iteration between synthesis and P&R (Place & Route) were integrated in the DSM design flow. This thesis mainly addresses the design of 8-bit CISC soft IP - 08C01, based on DSM technology.The research of this thesis proceeds on two sides: the standardization of IP design and DSM design technique. It can be divided into two main procedures: design phase and verification phase. The design phase includes the standardization of RTL coding, logic synthesis and place & route; the verification phase includes the function verification, static timing analysis and physical verification for 08C01. We use different commercial EDA tools in order to achieve betterimplementation in different design phase, which include Silicon Ensemble of Cadence, Design Compiler and Design Primer of Synopsys and so on.The research of this thesis contributes to the accumulation of the experience of IP design standardization for our country, and also provides the medium-scale IP's key technique based on the DSM technology. At the same time, it reaches higher performance than 6502 chip.