The Research And Design Of Cache Controller

Cache memory is a software transparent fast memory layer between the CPU and the main memory. It is so transparent that application developers do not need to think of its existence. Cache memory is constructed with high-speed static random access memory(SRAM), managed in a unit called cache line. The cycle time of SRAM can be as short as a few nanoseconds. This kind of performance can match the speed of microprocessor bus operation. The size of a cache line is usually a few processor words.Although SRAM is fast, it costs too much. A basic DRAM cell uses one transistor while an SRAM cell uses four. With the help of a cache memory all memory access requests,whenever possible, take place in cahce memory;main memory will be referred to only when it is necessary.Since a cache memory system can reduce the need for main memory access, It greatly reduces the potential memory access contention in shared memory Multiprocessor systems. It localizes memory access by isolation CPU bus traffic from memory bus traffic.This paper presents the logic circuit design of CCU for LX-1164 CPU chip, for CCU, data and instructions are stored in separate data and instruction caches. So it allows the processor to fetch instructions from the instruction cache and data from the data cache simultaneously. CCU contain a tag array and a data array. Dividing the cache into separating tag and data arrays reduces the access time of the cache. In order to keep the cache coherence , CCU adopts MOESI protocol.We adopt ASIC design technique, using advanced EDA tools to design and simulate CCU. At the same time, We propose an optimization methodology for power minimization by reconfiguring the organization of cache and changing the form of words stored in some cache lines.As this paper is related to technical secret of the linx company, so I can't give you information in details,I am so sorry about it.