IP Design And Implement For A Universal PWM Based On APB

In order to meet the requiements of the SoC chip integreating with the signal generator of three-phase pulse width modulation (PWM) in the motor control and Frequency conversion control of power electronics, this design provides the ASIC-based three-phase universal PWM IP core for SoC designers. This subject has completed the whole design and implement of the universal PWM IP Core based on APB, including RTL-level code for PWM, logic synthesis, design for testability (DFT), physical design and verification for the entire IP core.Firstly, this paper introduces AMBA2.0 APB specification. Based on the proposed framework and algorithm of PWM IP core, functional definition and partition are compeleted. And the key modules of the design is descripted, including period counting module, timing counting module, deadtime insert module and interrupt generation module. It also gives out the application of the PWM IP core. Secondly, it presents the steps and some results of the logic synthesis and DFT. Thirdly, physical design for PWM IP core is describled, including Floorplanning, Placement, Clock Tree Synthesis (CTS) and Routing. The corresponding steps and performance analysis of that are also gave out. Finally, it gives the results of verification for PWM IP core, including functional simulation, timing simulation, static timing analysis and formal verification. Those show that it meets the requirements of design specifications, and ultimately achieves timing closure.The Synopsys ASIC design tools are adoped with the Top-Down design methodology and RTL-level Verilog HDL, including Design Compiler applied for logic synthesis, DFT Compier used for DFT, IC Compiler applied for physical design, VCS and VIP used for logic function and timing simulation, PrimeTime applied for static timing analysis and using Formality completing formal verification.The main contribution of this subject provides a complete design flow of PWM core and resolves many critical technical difficulties, such as the design of deadtime insert module and timing counting module, floorplanning for hard core and so on. Not only this core can be used to three-phase PWM controlling but also single-phase controlling with modifying PWM core or configuring registers. It can configure multi-PWM generator using building block approach with this IP core, which demonstrates that this IP core is highly flexible and configurable. The perpose of this design is to provide soft-core, solid core and hard core with suitable functionality to meet the requirements of the designer, speeding up the progress of the design and high-performance.