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The Integrated Design Of Grating Digital Readout And Study Of Digital Locked-phase Loop

Posted on:2003-04-19Degree:MasterType:Thesis
Country:ChinaCandidate:M H YangFull Text:PDF
GTID:2168360095962091Subject:Measuring and Testing Technology and Instruments
Abstract/Summary:PDF Full Text Request
In this paper, measurement principle and development state of optical grating technology are briefly introduced. The advantages and disadvantages of several classical Moire fringe division methods are analyzed and compared with each other.Based on Phase-Locked Multi-Frequency division method ,and then a method of using LSI-ISP devices to design to realize integrating designation .This paper briefly introduced ISP devices and hardware description language VHDL ,and designs a kind of high integrated grating digital readout based on division theory and ISP design theory.The scheme combines the hardware design with software program, which have the features of modularization and all-purposes. The paper gives the basic constitute and function of each part of the hardware circuit, and the follow chart of the main-program and sub-program.The features of the new type of integration scheme can be described as follow: high division and easy debug are achieved in the scheme; accumulative total is used, and the discord of integer part and decimal part are avoided in the scheme; it can divide as well as detect direction; it can integrate the counter into ISP device and then evaluate the maxim frequency of the counter; it also integrate square wave and some logic devices into ISP device, and then improve integration, reliability, stability; and have the character of software designation instead of hardware designation and in-system programming, and it becomes very easy to modify the circuit and to extend the function.The digital phase-locked loop designed by ISP, which is adapted to optical grating readout is briefly introduced. System debugging and experiment procedure proves the feasibility of the integration theory. When the pitch of the grating sensor is 20μm, the system can achieve 20 division, and the system minim resolving power is 1μm.
Keywords/Search Tags:Grating, Division, VHDL, ISP, Phase-Locked Multi-frequency
PDF Full Text Request
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