Efficient Detection And Decoding Algorithms And Implementations For 5G Wireless Communication

As well known,large-scale multiple-input multiple-output(MIMO)becomes one key technology for 5th generation(5G)wireless communication systems,with its significant improvement in spectral efficiency,link reliability,and coverage over conventional MIMO?Recently,polar codes have been considered as a significant breakthrough in information theory because of their capacity-achieving capability for binary-input discrete memory-less channels(B-DMCs).Now they have been selected as the short coding scheme of control channels for 5G enhanced mobile broadband(eMBB)scenarios.In this paper,we mainly focus on the low-complexity detectors for large-scale MIMO systems and polar decoders,together with joint detection and decoding(JDD)methods for MIMO systems with polar codes.For the uplink large-scale MIMO systems,symbol-based belief propagation(BP)detection in real do-main is proposed.The mathematical expressions and analysis of message updating rules for independent identically distributed(i.i.d.)and correlated MIMO channels are given in detail.For large-scale MIMO sys-tems with correlation among transmitting antennas or loading factor ? = 1,damped BP algorithm is employed to improve the performance.In order to provide a good trade-off between performance and complexity,the adaptive message updating rule is first proposed,resulting in the adaptive BP detection.Compared with com-plex domain single-edge based BP(SE-BP),the proposed BP detection can achieve a significant performance improvement.For MIMO systems with correlation among transmitting and receiving antennas,simulation results have shown that the proposed adaptive BP detection achieves a significant complexity reduction com-pared to general BP detection with negligible performance loss.For i.i.d.and correlated fading channels with various antennas configurations,advantages of the proposed approach over existing BP detections as well as minimum mean square error(MMSE)approach have been demonstrated by thorough simulations.As a re-sult,the proposed BP detection is free of matrix inversion,then it can achieve the expected performance with low complexity.So it is suitable for various large-scale MIMO systems,especially for those with high-order modulations.For hardware implementation,we proposed a universal and hardware efficient BP detector,together with the detailed processing schedule analysis.Considering the hardware complexity and fault tolerance,the low-complexity BP detector via stochastic computation is first proposed.For MIMO systems with quadra-ture phase shift keying(QPSK)and quadrature amplitude modulation(QAM),the detailed logic structure for stochastic message updating and output decision is presented,where the re-randomizing and scaling-up schemes are employed to improve the performance.The performance of proposed stochastic BP detector improves with the increase of antenna number,finally achieves similar performance with deterministic one.According to the theoretical analysis,when antenna number increases,the hardware costs increase linearly,whereas the latency increases logarithmically.Compared with the latest detector,the hardware overheads of deterministic BP detector have a significant reduction.For MIMO systems with enough antennas,the s-tochastic BP detector has the comparable logic consumption as the deterministic ones,while the complicated arithmetic processing unit,such as digital signal processors(DSPs)is no need.When the antenna number increase,the proposed stochastic BP detector will show much more hardware advantage,while the system latency almost remain unchanged,resulting in the multiple throughput.As a consequence,the proposed s-tochastic BP detector is suitable for large-scale MIMO systems,where latency is not the primary concern,such as sensing networks and IoT.For practical applications where hardware complexity and system throughput bear the equal consideration,the deterministic BP detector is expected to be a promising candidate.For polar codes,two simplified sorting methods of path metrics for successive cancellation list(SCL)decoders,such as relaxed sorting(RS)and distributed sorting(DS)algorithms are proposed.For SCL decoder with list size L,both RS and DS algorithm reduce the complexity of path metric comparison from O(L2)to O(L),together with latency from kL2 to kL(k is a coefficient independent with L).SCL decoders with pro-posed RS and DS algorithms can achieve the similar decoding performance as that with direct sorting method.Then,the theoretical analysis of error propagation for SCL decoders in binary erasure channels(BEC)chan-nels is presented,followed by the simplified paths expansion,which reduces the complexity of path metrics sorting and memory management significantly.To achieve the comparable decoding performance with low-density parity-check(LDPC)and Turbo codes,the cyclic redundancy check(CRC)pre-coding is exploited,resulting in CA-SCL decoder.In addition,the segmented CA-SCL(SCA-SCL)decoder is proposed to dis-card the invalid paths as soon as possible,resulting in reduced average list size.The CA-SCL decoders with simplified paths expansion can achieve the same performance as the general CA-SCL decoders.And the proposed SCA-SCL decoders also perform well as CA-SCL decoders with negligible performance degrada-tion.Furthermore,the proposed simplified sorting algorithm,simplified paths expansion and segmented CRC strategy can be combined to achieve much lower complexity.For the overall system implementation of polar encoder and decoder,the parallel pipelined folding SCL decoding architecture is proposed.Based on the basic(?)-bit SC decoder,the folding and pipelined tech-niques,together with instruction set are employed to implement N-bit SC decoder.For conventional parallel and pipelined folding SCL decoding architectures,the theoretical analysis of system latency,mixed-nodes consumption and utilization is given.For the folded SC decoding architecture,the staged-based quantization scheme is proposed to reduce the average quantization bits with negligible performance loss.For(1024,512)polar code,the whole system of feed-back pipelined encoder and list adjustable SCL decoder with L = 2,4 are implemented on DE5-net with Altera Stratix V FPGA,together with the implementation results.When L = 4,the simplified DS2 algorithm is employed in sorting module,reducing the hardware complexity and latency significantly.The implemented system of polar encoder and decoder can achieve the expected decoding performance with low complexity and latency.Due to its inherent higher parallelism over polar SC decoder,polar BP decoder becomes more favorable for high throughput applications.By revealing the similarity between BP polar decoder and fast Fourier transform(FFT)processor,a universal design method of pipelined BP decoder is proposed.For example,both feed-forward and feed-back pipelined BP polar decoders are proposed along with detailed processing schedules.Based on the similarity of left-to-right and right-to-left message updating,the feed-forward and feed-back stage-based folding decoders are proposed to further reduce hardware complexity and improve hardware utilizations.For the existing and proposed four BP decoding architectures,the theoretical hardware complexity,system latency and throughput,together with hardware utilizations and efficiency are plotted as functions of code length,following by the analysis and comparison.The proposed feed-forward stage-based folding architecture achieves the highest hardware efficiency.Combining with implementation results,when the code length increases,both the proposed four architectures show hardware overheads and efficiency advantages over the previously-published architectures.In addition,all the proposed architectures are flexible to support different code lengths and rates,with acceptable complexity increase as code length.Furthermore,the pipelined design method of BP decoder offers us flexibility in achieving a desired trade-off between performance,throughput,latency,hardware consumption and utilization.For polar coded MIMO systems,the system setup for JDD is introduced,in which several channels are considered together.In order to avoid the redundant processing for invalid paths,the JDD algorithm based pruned search tree is proposed.For general cases,the mathematical expression for detection-decoding joint optimization is deduced.Then the joint optimization problem can be regarded as the breadth-first search(BFS)operation of a tree.According to the simulation results and complexity analysis,both the proposed JDD algorithms based on pruned tree and detection-decoding joint optimization achieves a significant performance improvement and complexity reduction,compared with the conventional separate detection and decoding(SDD)method.As a consequence,both the proposed JDD algorithms are promising for low-complexity and high-throughput applications.