Research On Encoding And Decoding Algorithm Of Polar Codes And VLSI Design

At present,the fifth generation mobile communication(5G)e MB B control channel has selected polar codes as the coding standard.Polar codes is the first channel coding method that has been mathematically proven to strictly reach the Shannon limit.The basis of the construction of the polar codes is channel polarization,that is,a highly reliable polarization channel transmits information bits,and a low reliability polarization channel transmits frozen bits.Because full polarization can only be achieved when the code length approaches infinity,the performance of polarized codes with limited co de lengths is not ideal.As the code length increases,the decoding latency and computational complexity also increase dramatically.The excellent performance of the channel coding system mainly depends on the performance of the decoder,so the research fo cus of this thesis is mainly on the optimization of low-latency and low-complexity decoding algorithms,and the VLSI design and implementation of the high performance decoder hardware architecture.The main research work is as follows:1.The high latency caused by the serial decoding characteristic of SC decoding algorithm is contrary to the high-speed information transmission target in wireless communication system.In the construction of polar codes,the frozen bits are preset at both the sender and the receiver,which can speed up the decoding speed.Therefore,this thesis analyzes the impact of frozen bits on the decoding speed in three levels: single frozen bit,frozen bit pair and frozen interval.Based on the frozen bit pair,an analysis method of de coding cycle and computational complexity is proposed,and a design mode of frozen bits suitable for pipeline tree decoding structure is proposed.Finally,the simplified SC decoder is implemented based on FPGA.Compared with previous research results,the decoding latency is optimized by 9.6% and the throughput is optimized by 10.4%.2.There are four types of special nodes in Fast-SSC(Fast simplified SC)decoding tree,which can be directly decoded in the proc ess of searching decoding tree.Therefore,by analyzing the characteristics of basic special nodes,this thesis proposes the possibility of expansion based on combined special nodes,and the rule that some combined special nodes can reuse the same special node decoder.According to the search rules of decoding tree,a method of cross node processing likelihood value is proposed to further speed up the decoding speed.The purpose of cross node processing likelihood value can be realized by adding a small number of logic circuits.In addition,the design method of reusing the same storage space for nodes of the same depth is proposed,which effectively saves the consumption of memory resources.Finally,based on the optimized fast SSC decoding algorithm,a high-performance Fast-SSC decoder architecture is proposed.FPGA implementation results show that compared with previous research results,the decoding latency is optimized by about 30%,the data throughput rate is optimized by at least 39.1%.