Study On Key Technologies In Real-time Micro-controller Chip Design

The design of real-time micro-controllers(RT-MCUs)has been demanded higher requirements from the gradual implementation of "carbon peaking and carbon neutrality" policy and the rapid development of new energy technology.On the one hand,the rising switching frequency of wide band gap power devices makes the size of electromagnetic components gradually miniaturized,and the corresponding problem is that the control accuracy of digital pulse width modulation(DPWM)decreases significantly,while the response time window of closed-loop control is compressed.On the other hand,on-chip data security has encountered new challenges due to the high commercial value of digital control algorithms and the incremental market of RT-MCUs today.In the background of the demand of higher accuracy in control,higher performance in computation and higher security in data,design improvements and innovations are needed for the control module,computation module and security module in RT-MCU.This dissertation focuses on the design of the RT-MCU and provides an intensive study and discussion of three key on-chip technologies:DPWM,transcendental function hardware accelerator,and data protection:1.In terms of control module research,a hybrid-DPWM architecture based on a dedicated delay chain is proposed for the design requirements of high-resolution DPWM,with significantly more precision than typical counter-comparator architectures and clock phase-shift architectures.In this architecture,a fully digital delay phase-locked loop(DLL)-based calibration module is designed for the device delay offset problem generated by the variation of process,voltage and temperature(PVT)condition.Matching the delay chain with the architecture enables highresolution double-edge independent control of DPWM,high-resolution phase shift function,and extended high-resolution DPWM period control,allowing better configuration flexibility of the module.The hybrid-DPWM has a 100ps time resolution at the standard operating point(TT corner)and in typical control configurations.2.The growth of control response time decreases to the control stability of the system,while the refinement of the control algorithm makes the central processing unit(CPU)computing time increase.In order to solve this contradiction,this dissertation designs the transcendental function unit(TFU)based on the analysis of various implementations of accelerators to improve the computational performance of RTMCU for closed-loop algorithms.TFU is designed with a multi-thread parallel architecture based on digital iterative algorithms,where each thread can independently complete the computation of sine,cosine,arc-tangent,logarithm,and exponential,resulting in a significant reduction in the time consumed by the CPU to execute multiple parallel closed-loop control algorithms.On this basis,for possible RT-MCU applications,TFU is designed with various configuration features to further reduce the time loss of system-level data transfer.In a typical industrial control scenario(e.g.motor PID control),the TFU takes only 0.42μs to compute 16 sine and cosine functions at 200MHz.3.In the selection of the RT-MCU root of trust,physical unclonable function(PUF)is a widely chosen security protection strategy because it does not store trust root data.However,the PUF technology with better reproducibility generally suffers from complex modules,long chip probe test(CP)time,and high integration difficulty.To deal with this drawback,this dissertation proposes a technical solution based on the stage gain biasing PUF(SGB-PUF).Compared with common SRAM PUFs,the SGBPUF achieves PUF biasing without external control conditions by dividing the powerup voltage into two main stages:low-noise amplification and latching.This is a pure circuit design method,which reduces the possibility that the output of the PUF is affected by thermal noise and thus improves the reproducibility of the PUF.The tapeout test chip results show that the SGB-PUF can achieve a bit error rate(BER)of<2%at the standard point and pass the basic randomness detection program without any aging biasing and pre-selection test,making it suitable for integration in RT-MCUs for root of trust.4.Considering that the application of SGB-PUF as a root of trust requires 100%reproducibility under non-typical conditions,this dissertation designs a highly errortolerant fuzzy extractor and a secure zone management module sample of RT-MCU.The fuzzy extractor consumes part of the non-volatile storage(NVM)space and achieves high fault tolerance with the help of look-up tables and optimization of BM algorithm.After completing the root of trust reconstruction,the zone management module achieves the feature of secure by assigning the control of on-chip storage read and write privileges by comparing the PUF response data to complete the SGB-PUF application.This dissertation discusses the design strategy of closed-loop control module and data protection key technologies around the design requirements of RT-MCU.A hybridDPWM architecture with background calibration at high PWM output frequency,a multi-threaded high-performance transcendental function unit architecture,an easily integrated SGB-PUF technology with fuzzy extractor and zone management module are proposed to provide a reference for future RT-MCU technology development.