High Performance Floating-point RISC-Ⅴ Processor Design Based On Transcendental Function Accelerator

Transcendental function refers to the nonlinear function that cannot be obtained by finite subquartic operation,which is widely used in power,motor control,the Internet of Things and other fields.Floating-point transcendental function operation is an important step in the process of executing arithmetic in a floating-point processor.Its operation speed directly affects the performance of a floating-point processor.At present,most of the research on transcendent function hardware accelerators only supports one transcendent function.When supporting multiple transcendent functions,it is usually accompanied by the waste of hardware resource,and the proper balance between calculation accuracy and calculation delay cannot be achieved.Furthermore,communication between the processor and the transcendent function hardware accelerator is typically accomplished via a coprocessor,resulting in a low overall processor performance.Therefore,it is of great significance to study and design a floating-point processor that supports transcending function operation.This paper presents the design architecture of a reconfigurable transcendental function hardware accelerator.Firstly,the piecewise lookup method combined with the binomial operation method was used to perform average segmentation and binomial fitting for the core computing units of each transcendent function,and a high-precision binomial coefficient lookup table was obtained so as to realize a high-precision and high-performance transcendent function hardware algorithm.Then,reconfigurable technology is used to plan the data path of each transcendent function,and the same core computing module is used to realize the hardware realization of sine,cosine,arctangent,exponential,and logarithmic functions so as to minimize the area of the transcendent function hardware accelerator.After testing,the accuracy of the hardware accelerator can be reached at7.268×10^-8,the calculation delay is 17.39 ns,and the area is 15062.91um².Compared with the sum of the hardware areas of the five transcendent functions realized independently,the area of the hardware accelerator is reduced by 30.48%.Based on the hardware accelerators mentioned above,a high-performance floating-point RISC-Ⅴ processor is designed for the fast operation of floating-point transcendence functions.We created a RISC-Ⅴ processor with a three-pipeline architecture that supports compression instructions,multiplication and division extension instructions,floating-point F extension instructions,and floating-point ZFINX extension instructions using the ASIP Designer development tool.Then custom instructions are added to support floating-point transcendental arithmetic.In addition,the multi-cycle processor description language is used to tightly couple the transcendental arithmetic hardware accelerator and the processor.A simulation platform for the RISC-Ⅴ processor was built,and functional verification was performed at the level of functional simulation and application testing,as well as PPA evaluation and optimization via logic synthesis and power analysis.The simulation results show that the maximum relative error of an exponential function is not greater than 5.125×10^-8,and the maximum absolute error of other transcendental functions is not greater than7.268×10^-8.Under the UMC 40nm process library,the operating frequency of the transcendental function floating-point processor is 350 MHz,the area is 57945.87um²,and the power consumption is 5.871mW.The results show that the performance of the proposed compact coupling design method is 23.59%higher than that of the coprocessor design method.In addition,compared with the state-of-the-art general-purpose RISC-Ⅴ floating-point processor,the performance of the proposed high-performance RISC-Ⅴ floating-point processor based on a transcendent function hardware accelerator is improved by about 4.34 times.