Investigation Of High Performance And Low Power Ge Field Effect Transistor (FET)

In recent decades,advances in information technology have greatly promoted the development of integrated circuit(IC)manufacturing.Metal oxide semiconductor field effect transistor(MOSFET)based on Si is the foundation of modern IC manufacturing technology.In the development process of the semiconductor industry,the performance boost(or the operation current enhancement)of Si MOSFET mainly depends on the downscaling of channel length.To overcome the short channel effect(SCE)by downscaling,many novel process technologies are proposed,such as strained-Si(s-Si),high-k metal gate(HKMG)and FinFET,which greatly improve the transistor performance.The latest transistors measure less than 20 nm for the channel length,but chip-makers plan to shrink them further still,which is becoming more and more difficult.MOSFETs with new high-mobility channel materials can achieve the increase of operation currents without shrinking the channel length,suggesting a new solution for the development of IC manufacturing.Ge,with the same family of Si,has been considered as one of the promising channel materials due to its high bulk mobilities and process compatibilities,and therefore,it is quite possible to be adopted in the future technology nodes.In this thesis,the source/drain(S/D)formation and gate stack engineering of Ge MOSFETs are systematically investigated.And then,some critical problems related with Ge based Tunneling FET(TFET)and Ferroelectric FET(FE-FET)are further discussed.The detailed research contents are listed as below.Firstly,new process technologies of S/D formation and gate stack engineering were explored and applied in the fabrication of Ge MOSFETs.As is know to all,it is difficult to obtain the Ge S/D junctions with low parasitic resistance,high ON/OFF ratio and shallow junction depth simultaneously,which is necessary for the high-performance Ge MOSFET,due to the low solubility and the large diffusion coefficient of dopants in Ge.Therefore,we explored a novel technique for the formation of ultra-shallow p+/n and n+/p junctions on Ge substrate using the spin-on dopant(SOD)followed by laser annealing(LA).It is found that the ultra-shallow junction depth of?20 nm and the high surface doping concentration of 1019 cm-3 have been achieved with improved ON/OFF ratio of?104.In addition,the NiGe/n-Ge Schottky junctions by the microwave annealing technique were proposed for the fabrication of high-performance Ge pMOSFETs.It is found that the Schottky-barrier height for holes is reduced to 0.03 eV,attributable to the suppression of metal-induced gap states-induced Fermi level pinning effect.As a result,an enhanced ON-current and a record high ON/OFF ratio of 104 were achieved in the Ge pMOSFETs with a NiGe metal S/D due to the extremely low resistance and significantly suppressed leakage current.On the other hand,the high-quality interface of high-k dielectrics on Ge are also indispensable for Ge MOSFETs.To control the influence of the unstable Ge oxide at high-k/Ge interface on device performance,the ultrathin HfO2/AlOx/GeOx/Ge gate-stacks were realized by ozone post oxidation(OPO).It is found that OPO increases the crystallization of HfO2,which sufficiently reduces the equivalent oxide thickness(EOT)without degrading the MOS interface quality.The dielectric strength of the HfO2/AlOx/GeOx/Ge gate-stack is also improved by using OPO.Besides,the semiconductor capping layer technique is another way to avoid the formation of GeO2/Ge interface.The MoS2/Ge structure were successfully fabricated in Ge p-and n-MOSFETs.The inversion holes and electrons are confined within Ge channels,which is attributable to the reasonable valence and conduction band offsets between the two-layer-thick MoS2 and Ge substrate.Consequently,MoS2 capped Ge MOSFETs exhibit much higher hole and electron mobilities by suppressing the scattering from the MOS interface.Power consumption is becoming a fundamental problem with downscaling the dimension of conventional Si MOSFET,since the supply voltage(Vdd)is limited by the minimum subthreshold swing(SS)of 60 mV/dec.Alternatively,tunneling FET(TFET)could break through this bottleneck thanks to the quantum mechanical band-to-band tunneling(BTBT).In this thesis,Ge p-and n-TFETs were demonstrated by dopant segregation(DS)NiGe S/D,which is featured with large Schottky-barrier height.From the low-temperature and fast I-V measurements,the NiGe Schottky junction interface traps are confirmed to be critical to the Ge TFET performance.Therefore,the interface traps near the NiGe/n-Ge interface were quantitatively characterized by low temperature conductance method.Fermi level pinning(FLP)effect is experimentally confirmed by metal induced gap states(MIGS).These NiGe/n-Ge interface traps can affect not only the SS properties of Ge TFETs but also the OFF-state of conventional Ge MOSFETs by trap assisted tunneling(TAT)currents.Recently,ferroelectric(FE)gated FETs have been widely reported in Ge MOSFETs,including Ge FE-FETs and Ge negative capacitance(NC)FETs as memory and logic devices,respectively.In both FE-FET and NC-FET,a FE insulator and linear dielectric(DE)insulator bilayer stack is applied as the gate structure.The necessity of such a linear DE layer is because an interfacial oxide layer between the semiconductor channel and FE insulator is required to improve the ferroelectric/semiconductor interface and meanwhile provides enough capacitance matching if the quasi-static negative capacitance(QSNC)concept is applied for the development of NC-FETs.However,The FE/DE stack is fundamentally different from a FE capacitor and a DE capacitor in series,since some interfacial coupling effects are involved.Charge trapping and de-trapping at the FE/DE interface are considered as the dominant interfacial coupling effects in the FE/DE stack.In this thesis,the charge behaviors of metal/FE/DE/metal structured capacitances are studied by the pulse measurements and conductance method.The trapped FE/DE interface charges are quantitatively characterized by using the previously proposed leakage-current-assist polarization switching mechanism.It is found that the FE/DE interface trap density is?1014 cm-2,suggesting that the FE/DE interface traps dominate the ferroelectric polarization switching.It means that,in the Ge ferroelectric gated FETs,the carrier density in the inversion channel is essentially not improved by the ferroelectric polarization switching effect due to the serious charge trapping at the FE/DE interface.In other words,the NC effect remains to be discussed.These interface traps will have a serious influence on the memory properties and reliabilities of FE-FETs.