An efficient array processor for image recognition

Many current high performance image processing systems use Single Instruction Single stream Multiple Data stream (SIMD) architectures. The SIMDDE c (SIMD designed by Daniel Eggers) architecture, is a circularly connected SIMD architecture designed for use in embedded systems. It has specialized hardware paths to facilitate high speed image rotation. Modifications of this architecture were compared for performance in increasing the overall speed of image recognition.;The full SIMDDE assigned each pixel of an image to a processing element. Adaptations of the SIMDDE system were considered in which fewer processing elements than pixels were utilized. In these adaptations only one-half or one-quarter of the full processing array were implemented in hardware. Two variants of the one-quarter system were considered. In one variant each of the processing elements were assigned a single pixel at a time, and in the other variant each processing element was assigned four pixels. Performance and quality comparisons were made between all of the variants. The results obtained were performance measurements, that would enable an engineer to choose the realization best suited for the needs of the system into which the architecture was to be embedded.;Performance comparisons were made between the full and adapted SIMDDE architectures, an unmodified SIMD architecture and two pipeline architectures. The methodology employed for these comparisons made use of an image recognition algorithm introduced by Castleman. It also involved verifying and extending the published analysis of Cantoni, Guerra, and Levialdi.;The evaluation of the SIMDDE architecture indicated that it would result in approximately a twofold improvement in speed, over a SIMD design which did not have the specialized paths for image rotation. Other evaluations indicated that there was only a small difference in speed between a system that implemented only half of the full logical system and a full implementation. It was noted that the one-quarter implementations were satisfactory for some applications, but were less desirable where greater speed of image recognition was critical.