A low power, embedded SIMD image processor architecture

Video compression is a compute intensive task that requires large processing capabilities. Various compression schemes exist for different communication channels. In particular, A SIMD processor architecture was developed for real time video compression of a 640 x 480 image at 30fps for transmission over a low bandwidth (<12Mbps) channel. Low power video compression is particularly important for “mobile” or “portable” communications. By developing an algorithm for low power video compression, it was also possible to design the system small enough to embed into a CMOS image sensor. The compression engine implements a modified form of vector quantization that significantly reduces computation time. The hardware was designed to be pitch matched to a CMOS image sensor and to demonstrate low power processing capability. The chip was fabricated using 0.6um CMOS technology. It demonstrates efficient integration of parallel processing elements and a novel memory architecture that allows a variety of image processing tasks. In particular, the processor architecture is capable of performing real-time video compression of 640 x 480 color image at 30frames/sec, dissipating 40mW at 2.5V with 10MHz clock.